1. Field of the Invention
This invention relates to a semiconductor memory and its test method, more particularly to improvements of automatic test functions of read only memory which permits electrical writing or erasing of information.
2. Description of the Related Art
Recently, the amount of processed data in an information processing system has been steadily increasing. Particularly in the field of voice and image processing, as microprocessors or central processing units of high ability and high performance are used, semiconductor memories are used as memories for storing their control programs.
As a typical example for such device, flash memory is widely known. Flash memory can be electrically programmed and moreover its programmed contents can be erased together.
Now, it will be useful to explain related arts of the invention. For example, as shown in FIG. 1, a programmable ROM (read only memory) which information can be electrically written to or erased from comprises the memory cells 1, a write/read (write and read) circuit 2, an address decoder 3 and an automatic control circuit 4.
The memory cells 1 comprises a memory cell matrix 1A, Y-gates 1B and a source control circuit 1C for erasing. A write/read circuit 2 comprises a sense/write amplifier 2A and an input/output buffer 2B. The address decoder 3 comprises a column address latch buffer 3A, a row address latch buffer 3B, a block address latch buffer 3C, a column address decoder 3D, a row address decoder 3E and a block address decoder 3F.
The automatic control circuit 4 comprises a command register 4A, a status register 4B, CE/OE/WE control logic 4C, a data comparator 4D, a write/erase selector 4E, a write/erase timing generator 4F and a clock generating section 4G. It is noted that the automatic control circuit 4 is provided with a self-test function.
As shown in a broken line circle of FIG. 1, each memory cell 1 includes a control gate CG and a floating gate FG, and stores data D by having charges injected into its floating gate FG.
In a data write operation of the memory, a control command for writing is input to the automatic control circuit 4 in the first place. When the writing high voltage VPP and an address AO-An are specified, charges are injected into the gate FG of the memory cell 1 at the location specified by the address decoder 3 and data D is written on the basis of the master clock signal by the write/read circuit 2.
In a data read operation, a read enable signal is first input to the automatic control circuit 4. And when normally used voltage VCC and an address AO-An are specified, the memory cell at the location specified by the address decoder 3 performs an "ON" operation, and therefrom is read data D on the basis of the master clock signal by the write/read circuit 2.
In a erase operation, a control command for erasing is first input to the automatic control circuit 4. When the erasing high voltage VPP and an address AO-An are specified, charges are removed from the gate FG of the memory cell 1 at the specified location and data D is erased on the basis of the master clock signal.
In a flash memory provided with a function for self-testing these fundamental operations, as shown in FIG. 2, the LSI tester 5 supplies a control command DIN to the memory 6. Then the flash memory 6, which is the target of the test, performs data write, read and erase operations according to a master clock signal and on the completion of a series of test operations, outputs the test results DOUT to the LSI tester 5.
It should be noted that a flash memory without a self-test function needs the supply of the control command DIN as well as test signals based on a predetermined algorithm.